The model and the experiment belong together
The electronics repository collects small designs that make digital behavior inspectable: adders, an adder/subtractor, counters, finite-state machines, and their testbenches. These are compact enough to follow from the HDL description to a waveform, with generated simulation artifacts alongside several examples.
jVerilog explored the tooling around that practice: a small interface around Icarus Verilog on Windows. The project belongs to the same body of work as the video explanations of compilation, simulation, and board-based experiments.
From schematic to post-layout behavior
The 2013 Synopsys tutorial series introduces schematic capture and HSpice simulation, then the relationship between Hercules DRC/LVS checks, StarRC parasitic extraction, and a post-layout testbench. A NAND example gives the tool sequence something tangible to operate on.
The tutorial itself notes that the NAND design is not a best-practice implementation. Its purpose is to explain the flow and the questions each stage answers. It should be read as educational material from that period, rather than a claim of a qualified production process.
A small example with a life beyond its repository
Washington University in St. Louis’s ESE461 VCS tutorial links directly to the repository’s adder directory on its reference page. It recommends the model and testbench examples as material for further exploration.
The cited material is the collection of Verilog models and testbenches, preserved with its original source history. It offers a concrete example of how small, inspectable teaching artifacts can remain useful beyond their original context.
From the workbench
Demonstrations & recordings
Synopsys: an introduction to the design flow
An introduction to HSpice, physical verification, parasitic extraction, and schematic-to-layout comparison through a NAND example.
Date not verified
Schematic capture and HSpice simulation
A practical continuation of the Synopsys tool flow, focused on entering and simulating a circuit.
Date not verified
Synopsys VCS on CentOS
A recorded walkthrough of the Verilog simulation environment using VCS on Linux.
Date not verified
jVerilog: a small Verilog IDE
A demonstration of a Windows interface around Icarus Verilog for a compact simulation workflow.
Evidence & further reading
Sources
- Tutorial for VCS · ESE461
Page 11 points readers to the electronics repository’s adder models and testbenches. This is a reference to the code, not authorship of the university tutorial.
- Electronics projects and HDL examples
Historical source repository with Verilog examples, testbenches, circuit exercises, and jVerilog.
- Verilog adder models and testbenches
The exact directory referenced by the ESE461 tutorial; public directory history includes December 2012 work.
- Synopsys tutorial · introduction and tool flow
Public description identifies HSpice, Hercules DRC/LVS, StarRC, and schematic/post-layout comparison. Educational demonstration, not a production IC qualification.